A conventional computer system includes a processor coupled to a variety of memory devices, including read-only memories (“ROMs”) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The system memory generally includes dynamic random access memory (“DRAM”), and in many modern computer systems includes synchronous DRAMs (“SDRAMs”) to enable the processor to access data at increasingly faster rates. One skilled in the art will appreciate, however, that a large speed disparity subsists between the operating speed of modern processors and that of modern SDRAMs. This speed disparity limits the rate at which the processor can access data stored in the SDRAMs, which is a common operation, and consequently limits the overall performance of the computer system. For example, modern processors, such as the Pentium® and Pentium II® microprocessors, are currently available operating at clock speeds of at least 400 MHz, while many SDRAMs operate at a clock speed of 66 MHz, which is a typical clock frequency for controlling system memory devices.
A solution to this operating speed disparity has been proposed in the form of a computer architecture known as a synchronous link architecture. In the synchronous link architecture, the system memory devices operate at much higher speeds and may be coupled to the processor either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, synchronous link memory devices receive command packets that include both control and address information. The synchronous link memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus.
A typical synchronous link dynamic random access memory (“SLDRAM”) memory device 16 is shown in block diagram form in FIG. 1. The memory device 16 includes a clock generator circuit 40 that receives a command clock signal CCLK and generates a large number of other clock and timing signals to control the timing of various operations in the memory device 16. The memory device 16 also includes a command buffer 46 and an address capture circuit 48 which receive an internal clock signal ICLK, a command packet CA<0:39> in the form of 4 packet words CA<0:9> applied sequentially on a 10 bit command-address bus CA, and a terminal 52 receiving a FLAG signal. A synchronization circuit 49 is part of the command buffer 46, and operates during a synchronization mode to synchronize the command clock signal CCLK and two data clock signals DCLK0 and DCKL1, as will be explained in more detail below.
A memory controller (not shown) or other device normally transmits the command packet CA<0:39> to the memory device 16 in synchronism with the command clock signal CCLK. The command packet CA<0:39> contains control and address information for each memory transfer. The FLAG signal identifies the start of a command packet CA<0:39>, and also signals the start of an synchronization sequence. The command buffer 46 receives the command packet CA<0:39> from the command-address bus CA, and compares at least a portion of the command packet to identifying data from an ID register 56 to determine if the command packet is directed to the memory device 16 or some other memory device (not shown). If the command buffer 46 determines that the command is directed to the memory device 16, it then provides the command to a command decoder and sequencer 60. The command decoder and sequencer 60 generates a large number of internal control signals to control the operation of the memory device 16 during a memory transfer.
The address capture circuit 48 also receives the command packet from the command-address bus CA and outputs a 20-bit address corresponding to the address information in the command packet. The address is provided to an address sequencer 64, which generates a corresponding 3-bit bank address on bus 66, a 10-bit row address on bus 68, and a 7-bit column address on bus 70. The row and column addresses are processed by row and column address paths, as will be described in more detail below.
One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The memory device 16 largely avoids this problem by using a plurality of memory banks 80, in this case eight memory banks 80a–h. After a read from one bank 80a, the bank 80a can be precharged while the remaining banks 80b–h are being accessed. Each of the memory banks 80a–h receives a row address from a respective row latch/decoder/driver 82a–h. All of the row latch/decoder/drivers 82a–h receive the same row address from a predecoder 84 which, in turn, receives a row address from either a row address register 86 or a refresh counter 88 as determined by a multiplexer 90. However, only one of the row latch/decoder/drivers 82a–h is active at any one time as determined by bank control logic 94 as a function of a bank address from a bank address register 96.
The column address on bus 70 is applied to a column latch/decoder 100, which supplies I/O gating signals to an I/O gating circuit 102. The I/O gating circuit 102 interfaces with columns of the memory banks 80a–h through sense amplifiers 104. Data is coupled to or from the memory banks 80a–h through the sense amps 104 and I/O gating circuit 102 to a data path subsystem 108 which includes a read data path 110 and a write data path 112. The read data path 110 includes a read latch 120 that stores data from the I/O gating circuit 102. In the memory device 16, 64 bits of data, which is designated a data packet, are stored in the read latch 120. The read latch then provides four 16-bit data words to an output multiplexer 122 that sequentially supplies each of the 16-bit data words to a read FIFO buffer 124. Successive 16-bit data words are clocked into the read FIFO buffer 124 by a clock signal RCLK generated from the internal clock signal ICLK. The 16-bit data words are then clocked out of the read FIFO buffer 124 by a clock signal obtained by coupling the RCLK signal through a programmable delay circuit 126. The programmable delay circuit 126 is programmed during synchronization of the memory device 16 so that the data from the memory device is received by a memory controller, processor, or other device (not shown) at the proper time. The FIFO buffer 124 sequentially applies the 16-bit data words to a driver circuit 128 which, in turn, applies the 16-bit data words to a data bus DQ. The driver circuit 128 also applies one of two data clock signals DCLK0 and DCLK1 to respective data clock lines 132 and 133. The data clocks DCLK0 and DCLK1 enable a device, such as a processor, reading the data on the data bus DQ to be synchronized with the data. Particular bits in the command portion of the command packet CA<0:39> determine which of the two data clocks DCLK0 and DCLK1 is applied by the driver circuit 128. It should be noted that the data clocks DCLK0 and DCLK1 are differential clock signals, each including true and complementary signals, but for ease of explanation, only one signal for each clock is illustrated and described.
The write data path 112 includes a receiver buffer 140 coupled to the data bus 130. The receiver buffer 140 sequentially applies 16-bit data words from the data bus DQ to four input registers 142, each of which is selectively enabled by a signal from a clock generator circuit 144. The clock generator circuit 144 generates these enable signals responsive to the selected one of the data clock signals DCLK0 and DCLK1. The memory controller or processor determines which data clock DCLK0 or DCLK1 will be utilized during a write operation using the command portion of a command packet applied to the memory device 16. As with the command clock signal CCLK and command packet CA<0:39>, the memory controller or other device (not shown) normally transmits the data to the memory device 16 in synchronism with the selected one of the data clock signals DCLK0 and DCLK1. The clock generator 144 is programmed during synchronization to adjust the timing of the clock signal applied to the input registers 142 relative to the selected one of the data clock signals DCLK0 and DCLK1 so that the input registers 142 can capture the write data at the proper times. In response to the selected data clock DCLK0 or DCLK1, the input registers 142 sequentially store four 16-bit data words and combine them into one 64-bit write packet data applied to a write FIFO buffer 148. The write FIFO buffer 148 is clocked by a signal from the clock generator 144 and an internal write clock WCLK to sequentially apply 64-bit write data to a write latch and driver 150. The write latch and driver 150 applies the 64-bit write data packet to one of the memory banks 80a–h through the I/O gating circuit 102 and the sense amplifiers 104.
A typical command packet CA<0:39> for the SLDRAM 16 is shown in FIG. 2 and is formed by 4 packet words CA<0:9>, each of which contains 10 bits of data. As explained above, each 10-bit packet word CA<0:9> is applied on the command-address bus CA including the 10 lines CA0–CA9, and coincident with each packet word CA<0:9> a FLAG bit is applied on the FLAG line 52. As previously discussed, during normal operation the FLAG bit is high to signal the start of a command packet CA<0:39>, and thus is only high coincident with the first packet word CA<0:9> of the command packet. In FIG. 2, the four packet words CA<0:9> comprising a command packet CA<0:39> are designated PW1–PW4. The first packet word PW1 contains 7 bits of data identifying the memory device 16 that is the intended recipient of the command packet. The memory device 16 has a unique ID code stored in the ID register 56, and this code is compared to the 7 ID bits in the first packet word PW1. Thus, although all of the memory devices 16 in a synchronous link system will receive the command packet CA<0:39>, only the memory device 16 having an ID code that matches the 7 ID bits of the first packet word PW1 will respond to the command packet.
The remaining 3 bits of the first packet word PW1 as well as 3 bits of the second packet word PW2 comprise a 6 bit command. Typical commands are read and write in a variety of modes, such as accesses to pages or banks of memory cells. The remaining 7 bits of the second packet word PW2 and portions of the third and fourth packet words PW3 and PW4 comprise a 20 bit address specifying a bank, row and column address for a memory transfer or the start of a multiple bit memory transfer. In one embodiment, the 20-bit address is divided into 3 bits of bank address, 10 bits of row address, and 7 bits of column address. Although the command packet CA<0:39> shown in FIG. 2 is composed of 4 packet words PW1–PW4 each containing up to 10 bits, it will be understood that a command packet may contain a lesser or greater number of packet words, and each packet word may contain a lesser or greater number of bits.
As mentioned above, an important goal of the synchronous link architecture is to allow data transfer between a processor and a memory device to occur at a significantly faster rate. However, as the rate of data transfer increases, it becomes more difficult to maintain synchronization between signals transmitted to the memory device 16. For example, as mentioned above, the command packet CA<0:39> is normally transmitted to the memory device 16 in synchronism with the command clock signal CCLK, and the data is normally transmitted to the memory device 16 in synchronism with the selected one of the data clock signals DCLK0 and DCLK1. However, because of unequal signal delays and other factors, the command packet CA<0:39> may not arrive at the memory device 16 in synchronism with the command clock signal CCLK, and the data may not arrive at the memory device 16 in synchronism with the selected data clock signal DCLK0 or DCLK1. Moreover, even if these signals are actually coupled to the memory device 16 in synchronism with each other, they may loose synchronism once they are coupled to circuits within the memory device. For example, internal signals require time to propagate to various circuitry in the memory device 16, differences in the lengths of signal routes can cause differences in the times at which signals reach the circuitry, and differences in capacitive loading of signal lines can also cause differences in the times at which signals reach the circuitry. These differences in arrival times can become significant at high speeds of operation and eventually limit the operating speed of memory devices.
The problems associated with varying arrival times are exacerbated as timing tolerances become more restricted with higher data transfer rates. For example, if the internal clock ICLK derived from the command clock CCLK does not latch each of the packet words CA<0:9> comprising a command packet CA<0:39> at the proper time, errors in the operation of the memory device may -result. Similarly, data errors may result if internal signals developed responsive to the data clocks DCLK0 and DCLK1 do not latch data applied on the data bus DQ at the proper time. Thus, the command clock CCLK and data clocks DCLK0 and DCLK1 must be synchronized to ensure proper operation of the SLDRAM 16. One skilled in the art will understand that when synchronization of the clock signals CCLK, DCLK0, and DCLK1 is discussed, this means the adjusting of the timing of respective internal clock signals derived from these respective external clock signals so the internal clock signals can be used to latch corresponding digital signals at optimum times. For example, the command clock signal CCLK is synchronized when the timing of the internal clock signal ICLK relative to the command clock signal CCLK causes packet words CA<0:9> to be latched at the optimum time.
To synchronize the clock signals CCLK, DCLK0, and DCLK1, the memory controller (not shown) places the memory device 16 in a synchronization mode by applying a 15 bit repeating pseudo-random bit sequence on each line of the command-address bus CA, data bus DQ, and on the FLAG line 52. One of the 15 bit pseudo-random bit sequences that may be applied is shown below in Table 1:
TABLE 1FLAG111101011001000CA<9>000010100110111CA<8>111101011001000CA<7>000010100110111MMMMMMMMMMMMMMMMCA<0>111101011001000DQ<15>000010100110111DQ<14>111101011001000MMMMMMMMMMMMMMMMDQ<0>111101011001000As seen in Table 1, the 15-bit pseudo-random bit sequence is complemented on adjacent lines of the command-address bus CA and data bus DQ. In the following description, only the synchronization of the ICLK signal will be described, so only the bit sequences applied on the command-address bus CA and FLAG line 52, which are latched in response to the ICLK signal, will be discussed. Furthermore, the bit sequences applied on the command-address bus CA and FLAG line 52 may alternatively be referred to as bit streams in the following discussion. However, the DCLK0 and DCLK1 signals are synchronized in essentially the same manner.
The memory device 16 captures the bits applied on the lines CA0–CA9 and the FLAG line 52 in response to the ICLK signal, and the synchronization circuit 49 places the memory device 16 in the synchronization mode when it detects two consecutive high (i.e., two 1's) on the FLAG bit. Recall, during normal operation, only a single high FLAG bit is applied coincident with the first packet word CA<0:9> of the command packet CA<0:39>. After the synchronization circuit 49 places the SLDRAM 16 in the synchronization mode, the SLDRAM 16 continues capturing packet words CA<0:9> applied on the bus CA and the coincident applied FLAG bits in response to the ICLK signal. After four packet words CA<0:9> and the accompanying four FLAG bits have been captured, the synchronization circuit 49 compares the captured bits to their expected values. The synchronization circuit 49 determines the expected values from the known values of the 15 bit repeating pseudo-random bit sequence. For example, from Table 1, after the first four bits 1111 of the FLAG bit are captured, the circuit 49 calculates the expected data for the next four captured bits as 0101, and the next four as 1001, and so on. In operation, the synchronization circuit 49 adjusts the phase of the ICLK signal before capturing the next group of bits. For example, a first phase for the ICLK signal is used to capture the first four FLAG bits 1111, a second phase for the FLAG bits 0101, a third phase for the FLAG bits 1001, and so on. Each phase resulting in successful capture of the command packet CA<0:39> is recorded by the synchronization circuit 49, and thereafter one of these phases is selected to be utilized during normal operation of the memory device 16.
FIG. 3 illustrates a potential problem encountered when synchronizing the memory device 16 as described above. In FIG. 3, the 15-bit pseudo-random bit pattern applied for the FLAG bit is shown by way of example, but the same potential problem exists for the bit sequences on the lines CA0–CA9 as well. The top sequence is the actual bit pattern applied for the FLAG bit, with the bits arranged in groups of 4 in respective capture groups C1–C15. Each capture group C1–C15 corresponds to the four FLAG bits captured coincident with four corresponding packet words CA<0:9>. The capture group C1 corresponds to the start of the bit sequence, and, as should be noted, the two consecutive ones for the FLAG bit place the memory device 16 in the synchronization mode. Ideally, the SLDRAM 16 captures the first group C1 of 4 FLAG bits 1111, then the group C2 of 0101, then group C3 of 1001, and so on. During ideal operation, the capture group C1 of 1111 is captured first, placing the memory device 16 in synchronization mode, and thereafter, the synchronization circuit 49 (FIG. 1) provides the expected data for the subsequent capture groups C2-CN. In other words, the synchronization circuit 49 expects the captured FLAG bits for C2 to equal 0101, for C3 to equal 1001, and so on.
If the capturing of the FLAG bit sequence is shifted, however, as shown in the lower bit sequence of FIG. 3, the synchronization circuit 49 may use the improper expect data for capture groups C2–C15. For example, assume the actual bits captured for groups C1–C5 are as shown in the lower bit sequence of FIG. 3. In response to the bits 1101 captured for group C1, the memory device 16 enters the synchronization mode of operation due to the two high FLAG bits. After this, the synchronization circuit 49 expects group C2 bits to equal 0101, group C3 bits to equal 1001, and so on for groups C4–C15 as indicated by the ideal FLAG data shown in the top bit sequence. Instead, however, the group C2 bits equal 0110 for the shifted FLAG sequence, and the group C3 equals 0100, and so on, such that each of the respective capture groups C1-C15 in the shifted FLAG bit sequence corresponds to four bits in the top bit sequence shifted to the left by two bits, as indicated by dotted lines 30. This could occur, for example, when the memory device 16 fails to latch the first two ones applied on the FLAG line 52 due to delays in CCLK signal applied by the controller. When the FLAG bit sequence is shifted, the values of subsequent capture groups result in the synchronization circuit 49 determining the FLAG bit is not being correctly captured, when in fact the FLAG bit pattern is being successfully captured but is merely shifted by a random number of bits.
There is a need for generating accurate expect data when capturing a pseudo-random bit sequence during synchronization of packetized memory device. In addition, it should be noted that while the above discussion is directed towards packetized memory devices such as SLDRAMs, the concepts apply to other types of integrated circuits as well, including other types of memory devices and communications circuits.